Description
Design of 3D Integrated Circuits and Systems
Devices, Circuits, and Systems Series
Coordinator: Sharma Rohit
Language: English
Subjects for Design of 3D Integrated Circuits and Systems:
Keywords
Power Consumption; Vertical Interconnects; Three-Dimensional Device; Inductive Coupling; 3D Device; Cpu Core; Low-Power Testing; Scan Chains; Through-Silicon; GPU Core; Carbon Nanotube Through-Silicon; Digital CMOS; Copper Nanotube Through-Silicon; ATPG Tool; Interface; Clock Gaters; Inductive-Coupling; Chip Stack; ThruChip; SEM Image; Inductive-Coupling ThruChip Interface; Equivalent Electrical Model; Three-Dimensional Network-on-Chip; Electrothermal Simulation; Three-Dimensional Network; Si CMOS; 3D Network; Voltage Droop; Multidrop Bus; NAND Flash Memory; Three-Dimensional System; Delay Fault; 3D System; Transition Delay Fault; NoC Architecture; Die Stack; Microprocessor; Kinetic Inductance; 3D Integrated Circuit; Cycle Time; Three-Dimensional IC; Underfill Material; Three-Dimensional Integrated Circuit; Test Vectors; 3D IC; IC; Integrated Circuit; CMOS Integration; Integration; Graphics Processing Core; IMC Bonding; TSV Bonding; Three-Dimensional; 3D Integration; Integration Technology; TSVs; Through-Silicon Vias; Network-on-Chip; 3D Network-on-Chip; Interconnect Technology; Thermal Reliability; Thermal Management; Microprocessor Integration; Graphics Processing Core Integration; Three-Dimensional Complementary Metal–Oxide–Semiconductor Integration; 3D CMOS Integration; 3D Integration Technology; Three-Dimensional Integration; 3D Circuit; Three-Dimensional Circuit; Katsuyuki Sakuma; Ronald J; Gutmann; Jian-Qiang Lu; Deepak C; Sekar; Ballapuram Chinnakrishnan; Shivam Priyadarshi; Jianchen Hu; Michael B; Steer; Paul D; Franzon; W; Rhett Davis; Francesco Zanini; Sharma Rohit; Kiyoung Choi; Sung Kyu Lim; Krzysztof Iniewski; Lin Xijiang; Wen Xiaoqing; Xiang Dong
Publication date: 09-2020
· 15.6x23.4 cm · Paperback
Publication date: 11-2014
324 p. · 15.6x23.4 cm · Hardback
Description
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/li>Biography
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Three-dimensional (3D) integration of microsystems and subsystems has become essential to the future of semiconductor technology development. 3D integration requires a greater understanding of several interconnected systems stacked over each other. While this vertical growth profoundly increases the system functionality, it also exponentially increases the design complexity.
Design of 3D Integrated Circuits and Systems tackles all aspects of 3D integration, including 3D circuit and system design, new processes and simulation techniques, alternative communication schemes for 3D circuits and systems, application of novel materials for 3D systems, and the thermal challenges to restrict power dissipation and improve performance of 3D systems. Containing contributions from experts in industry as well as academia, this authoritative text:
- Illustrates different 3D integration approaches, such as die-to-die, die-to-wafer, and wafer-to-wafer
- Discusses the use of interposer technology and the role of Through-Silicon Vias (TSVs)
- Presents the latest improvements in three major fields of thermal management for multiprocessor systems-on-chip (MPSoCs)
- Explores ThruChip Interface (TCI), NAND flash memory stacking, and emerging applications
- Describes large-scale integration testing and state-of-the-art low-power testing solutions
Complete with experimental results of chip-level 3D integration schemes tested at IBM and case studies on advanced complementary metal?oxide?semiconductor (CMOS) integration for 3D integrated circuits (ICs), Design of 3D Integrated Circuits and Systems is a practical reference thatnot only covers a wealth of design issues encountered in 3D integration but also demonstrates their impact on the efficiency of 3D systems.
3D Integration Technology with TSV and IMC Bonding. Wafer-Level 3D ICs for Advanced CMOS Integration. Integration of Graphics Processing Cores with Microprocessors. Electrothermal Simulation of 3D ICs. Thermal Management in 3D ICs/Systems. Emerging Interconnect Technologies for 3D Networks-on-Chips. Inductive-Coupling ThruChip Interface for 3D Integration. Fabrication and Modeling of Copper and Carbon Nanotube-Based Through-Silicon Via. Low-Power Testing for 2D/3D Devices and Systems.
Rohit Sharma is faculty at the Indian Institute of Technology Ropar, Punjab. He previously worked as a post-doctoral researcher at Seoul National University, South Korea and at Georgia Institute of Technology, Atlanta, USA. Dr. Sharma has authored/co-authored over 50 journal and conference publications, one book, one book chapter, two patents/copyrights, and several invited talks. He was a recipient of the Brain Korea Research Fellowship (2010), the Indo-US Research Fellowship (2011), and Best Paper Awards in ASQED 2010 and GIT 2011 conferences. An IEEE and ACM member, he has served as a journal referee and committee member/session co-chair on multiple occasions.
