Hybrid Fault Tolerance in Embedded Processors, 2014
Techniques to Detect Transient Faults

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Language: Anglais
Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors
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Support: Imprimé à la demande

Hybrid Fault Tolerance in Embedded Processors. Techniques to Detect Transient Faults
Publication date:
94 p. · 15.5x23.5 cm · Hardback
This book describes fault tolerance techniques based on software and hardware to create hybrid techniques that reduce overall performance degradation and increase error detection associated with applications implemented in embedded processors. Coverage begins with an extensive discussion of the current state-of-the-art in fault tolerance techniques. The authors then discuss the best trade-off between software-based and hardware-based techniques, which increase existing fault detection rates up to 100%, while maintaining low performance overheads.
Background.- Fault tolerance Techniques for Processors.- Proposed Techniques to Detect Transient Faults in Processors.- Simulation Fault Injection Experimental Results.- Configuration Bitstream Fault Injection Experimental Results.- Radiation Experimental Results.

Provides a comprehensive overview of state-of-the art fault tolerance techniques based on software, hardware, and hybrid techniques

Discusses the effects of radiation on modern integrated circuits

Introduces novel hybrid fault tolerance techniques for reconfigurable FPGAs and ASICs

Enables readers to use techniques with lower performance degradation, area occupation, and memory usage