Computer Organization and Design RISC-V Edition (2nd Ed.)
The Hardware Software Interface
The Morgan Kaufmann Series in Computer Architecture and Design Series

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Language: English

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736 p. · 19x23.4 cm · Paperback
Computer Organization and Design RISC-V Edition: The Hardware Software Interface, Second Edition, the award-winning textbook from Patterson and Hennessy that is used by more than 40,000 students per year, continues to present the most comprehensive and readable introduction to this core computer science topic. This version of the book features the RISC-V open source instruction set architecture, the first open source architecture designed for use in modern computing environments such as cloud computing, mobile devices, and other embedded systems. Readers will enjoy an online companion website that provides advanced content for further study, appendices, glossary, references, links to software tools, and more.

1. Computer Abstractions and Technology 2. Instructions: Language of the Computer 3. Arithmetic for Computers 4. The RISC-V Processor 5. Large and Fast: Exploiting Memory Hierarchy 6. Parallel Processors from Client to Cloud

Appendix A. The Basics of Logic Design B. Graphics and Computing GPUs C. Mapping Control to Hardware D. A Survey of RISC Architectures

David Patterson is the Pardee Professor of Computer Science, Emeritus at the University of California at Berkeley, which he joined after graduating from UCLA in 1977.His teaching has been honored by the Distinguished Teaching Award from the University of California, the Karlstrom Award from ACM, and the Mulligan Education Medal and Undergraduate Teaching Award from IEEE. Prof. Patterson received the IEEE Technical Achievement Award and the ACM Eckert-Mauchly Award for contributions to RISC, and he shared the IEEE Johnson Information Storage Award for contributions to RAID. He also shared the IEEE John von Neumann Medal and the C & C Prize with John Hennessy. Like his co-author, Prof. Patterson is a Fellow of the American Academy of Arts and Sciences, the Computer History Museum, ACM, and IEEE, and he was elected to the National Academy of Engineering, the National Academy of Sciences, and the Silicon Valley Engineering Hall of Fame. He served on the Information Technology Advisory Committee to the U.S. President, as chair of the CS division in the Berkeley EECS department, as chair of the Computing Research Association, and as President of ACM. This record led to Distinguished Service Awards from ACM, CRA, and SIGARCH.
ACM named John L. Hennessy a recipient of the 2017 ACM A.M. Turing Award for pioneering a systematic, quantitative approach to the design and evaluation of computer architectures with enduring impact on the microprocessor industry. John L. Hennessy is a Professor of Electrical Engineering and Computer Science at Stanford University, where he has been a member of the faculty since 1977 and was, from 2000 to 2016, its tenth President. Prof. Hennessy is a Fellow of the IEEE and ACM; a member of the National Academy of Engineering, the National Academy of Science, and the American Philosophical Society; and a Fellow of the American Academy of Arts and Sciences. Among his many awards are the 2001 Eckert-Mauchly Award for his contributions to RISC techn
  • Covers parallelism in-depth, with examples and content highlighting parallel hardware and software topics
  • Focuses on 64-bit address, ISA to 32-bit address, and ISA for RISC-V because 32-bit RISC-V ISA is simpler to explain, and 32-bit address computers are still best for applications like embedded computing and IoT
  • Includes new sections in each chapter on Domain Specific Architectures (DSA)
  • Provides updates on all the real-world examples in the book