High Performance Parallelism Pearls Volume Two
Multicore and Many-core Programming Approaches

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Language: English

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592 p. · 19x23.3 cm · Paperback

High Performance Parallelism Pearls Volume 2 offers another set of examples that demonstrate how to leverage parallelism. Similar to Volume 1, the techniques included here explain how to use processors and coprocessors with the same programming ? illustrating the most effective ways to combine Xeon Phi coprocessors with Xeon and other multicore processors. The book includes examples of successful programming efforts, drawn from across industries and domains such as biomed, genetics, finance, manufacturing, imaging, and more. Each chapter in this edited work includes detailed explanations of the programming techniques used, while showing high performance results on both Intel Xeon Phi coprocessors and multicore processors. Learn from dozens of new examples and case studies illustrating "success stories" demonstrating not just the features of Xeon-powered systems, but also how to leverage parallelism across these heterogeneous systems.

  1. Introduction
  2. Numerical Weather Prediction Optimization
  3. WRF Goddard Microphysics Scheme Optimization
  4. Pairwise DNA Sequence Alignment Optimization
  5. Accelerated Structural Bioinformatics for Drug Discovery
  6. Amber PME Molecular Dynamics Optimization
  7. Low-Latency Solutions for Financial Services Applications
  8. Parallel Numerical Methods in Finance
  9. Wilson Dslash Kernel from Lattice QCD Optimization
  10. Cosmic Microwave Background Analysis: Nested Parallelism
  11. Visual Search Optimization
  12. Radio Frequency Ray Tracing
  13. Exploring Use of the Reserved Core
  14. High Performance Python Offloading
  15. Fast Matrix Computations on Heterogeneous Streams
  16. MPI-3 Shared Memory Programming Introduction
  17. Coarse-Grained OpenMP for Scalable Hybrid Parallelism
  18. Exploiting Multilevel Parallelism in Quantum Simulations
  19. OpenCL: There and Back Again
  20. OpenMP Versus OpenCL: Difference in Performance?
  21. Prefetch Tuning Optimizations
  22. SIMD Functions Via OpenMP
  23. Vectorization Advice
  24. Portable Explicit Vectorization Intrinsics
  25. Power Analysis for Applications and Data Centers
Jim Jeffers was the primary strategic planner and one of the first full-time employees on the program that became Intel ® MIC. He served as lead SW Engineering Manager on the program and formed and launched the SW development team. As the program evolved, he became the workloads (applications) and SW performance team manager. He has some of the deepest insight into the market, architecture and programming usages of the MIC product line. He has been a developer and development manager for embedded and high performance systems for close to 30 years.
James Reinders is a senior engineer who joined Intel Corporation in 1989 and has contributed to projects including the world’s first TeraFLOP supercomputer (ASCI Red), as well as compilers and architecture work for a number of Intel processors and parallel systems. James has been a driver behind the development of Intel as a major provider of software development products, and serves as their chief software evangelist. James has published numerous articles, contributed to several books and is widely interviewed on parallelism. James has managed software development groups, customer service and consulting teams, business development and marketing teams. James is sought after to keynote on parallel programming, and is the author/co-author of three books currently in print including Structured Parallel Programming, published by Morgan Kaufmann in 2012.
  • Promotes write-once, run-anywhere coding, showing how to code for high performance on multicore processors and Xeon Phi
  • Examples from multiple vertical domains illustrating real-world use of Xeon Phi coprocessors
  • Source code available for download to facilitate further exploration