Logic synthesis

Author:

Language: Anglais

47.75 €

Subject to availability at the publisher.

Add to cartAdd to cart
Publication date:
448 p. · 22.9x16 cm · Hardback
This guide to logic synthesis techniques spotlights not only the synthesis of two-level, multi-level and combinational circuits but also their testability. It should be a useful reference for designers of next generation VLSI chips.
Introduction. Translation from HDL Descriptions. Two-Level Combinatorial Circuits. Synthesis of Two-Level Circuits. Testability of Two-Level Circuits. Multilevel Combinational Circuits. Synthesis of Multilevel Circuits. Delay of Multilevel Circuits. Testability of Multilevel Circuits. Ongoing Work and Future Directions.