MIPS risc architecture (Paper)

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Language: Anglais
Cover of the book MIPS risc architecture (Paper)

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774 p. · 23.4x17.8 cm · Paperback
A complete reference manual to the MIPS RISC architecture, this book describes the user Instruction Set Architecture (ISA), by the R2000, R3000, R4000, and R6000 (collectively known as the R-Series) processors, together with an extension to this ISA. Focusing on the new R4000 and R6000 chips, this book is organized into two major sections: Chapters 1 through 6 describe the characteristics of the CPU, while Chapter 7 through 9 describe the Floating Point Unit (FPU). This book describes the general characteristics and capabilities of each RISC processor, along with a description of the programming model, memory management unit (MMU), and the registers associated with each processor. Also included is an overview of the underlying concepts that distinguish RISC architecture from Complex Instruction Set Computer (CISC) architecture.
  1. RISC Architecture: An Overview
  2. MIPS Processor Architecture Overview
  3. CPU Instruction Set Summary
  4. Memory Management System
  5. Caches
  6. Exception Processing
  7. FPU Overview
  8. FPU Instruction Set Summary and Instruction Pipeline
  9. Floating Point Exceptions
  10. Appendixes
  11. Index
  • describes the user Instruction Set Architecture (ISA), as implemented by the R2000, R3000, R4000, and R6000 (collectively known as the R-Series) processors, together with an extension to this ISA.
  • describes the general characteristics and capabilities of each RISC processor, along with a description of the programming model, memory management unit (MMU), and the registers associated with each processor.
  • includes an overview of the underlying concepts that distinguish RISC architecture from Complex Instruction Set Computer (CISC) architecture.