Three-Dimensional Integrated Circuit Design, 2010
EDA, Design and Microarchitectures

Integrated Circuits and Systems Series

Coordinators: Xie Yuan, Cong Jingsheng Jason, Sapatnekar Sachin

Language: English
Cover of the book Three-Dimensional Integrated Circuit Design

Subject for Three-Dimensional Integrated Circuit Design

158.24 €

Subject to availability at the publisher.

Add to cartAdd to cart
Publication date:
284 p. · 15.5x23.5 cm · Hardback
We live in a time of great change. In the electronics world, the last several decades have seen unprecedented growth and advancement, described by Moore?s law. This observation stated that transistor density in integrated circuits doubles every 1. 5?2 years. This came with the simultaneous improvement of individual device perf- mance as well as the reduction of device power such that the total power of the resulting ICs remained under control. No trend remains constant forever, and this is unfortunately the case with Moore?s law. The trouble began a number of years ago when CMOS devices were no longer able to proceed along the classical scaling trends. Key device parameters such as gate oxide thickness were simply no longer able to scale. As a result, device o- state currents began to creep up at an alarming rate. These continuing problems with classical scaling have led to a leveling off of IC clock speeds to the range of several GHz. Of course, chips can be clocked higher but the thermal issues become unmanageable. This has led to the recent trend toward microprocessors with mul- ple cores, each running at a few GHz at the most. The goal is to continue improving performance via parallelism by adding more and more cores instead of increasing speed. The challenge here is to ensure that general purpose codes can be ef?ciently parallelized. There is another potential solution to the problem of how to improve CMOS technology performance: three-dimensional integrated circuits (3D ICs).
3D Process Technology Considerations.- Thermal and Power Delivery Challenges in 3D ICs.- Thermal-Aware 3D Floorplan.- Thermal-Aware 3D Placement.- Thermal Via Insertion and Thermally Aware Routing in 3D ICs.- Three-Dimensional Microprocessor Design.- Three-Dimensional Network-on-Chip Architecture.- PicoServer: Using 3D Stacking Technology to Build Energy Efficient Servers.- System-Level 3D IC Cost Analysis and Design Exploration.
Contains a thorough survey of the field for 3D EDA tools Provides a clear understanding of the need of adopting 3D IC design, and an overview of existing techniques to help 3D IC design Covers the motivation and intuition behind the techniques that helps 3D design, leading to the ability to better take advantage of the 3D IC design Includes fundamental knowledge of 3D process, and 3D EDA tools that can help the architectural level design exploration Provides a understanding of the benefits and limitations of the 3D design at the architectural level, leading to novel 3D microarchitecture design Includes supplementary material: sn.pub/extras