VLSI Test Principles and Architectures
Design for Testability
Authors: Wang Laung-Terng, Wu Cheng-Wen, Wen XiaoqingLanguage: Anglais
In Print (Delivery period: 14 days).Add to cart the livre of Wang Laung-Terng, Wu Cheng-Wen, Wen Xiaoqing
776 p. · 19.1x23.5 cm · Hardback
- Most up-to-date coverage of design for testability.
- Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books.
- Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
Chapter 2 – Design for Testability
Chapter 3 – Logic and Fault Simulation
Chapter 4 – Test Generation
Chapter 5 – Logic Built-In Self-Test
Chapter 6 – Test Compression
Chapter 7 – Logic Diagnosis
Chapter 8 – Memory Testing and Built-In Self-Test
Chapter 9 – Memory Diagnosis and Built-In Self-Repair
Chapter 10 – Boundary Scan and Core-Based Testing
Chapter 11 – Analog and Mixed-Signal Testing
Chapter 12 – Test Technology Trends in the Nanometer Age
SECONDARY: Undergraduate and graduate-level courses in Electronic Testing, Digital Systems Testing, Digital Logic Test & Simulation, and VLSI Design.
These books may interest you
Digital system test and testable design: using hdl models and architectures (hardback)Using HDL Models and Architectures 73.93 €