Analog Device-Level Layout Automation, Softcover reprint of the original 1st ed. 1994
The Springer International Series in Engineering and Computer Science Series, Vol. 263

This book presents a detailed summary of research on automatic layout of device-level analog circuits that was undertaken in the late 1980s and early 1990s at Carnegie Mellon University. We focus on the work behind the creation of the tools called KOAN and ANAGRAM II, which form part of the core of the CMU ACACIA analog CAD system. KOAN is a device placer for custom analog cells; ANANGRAM II a detailed area router for these analog cells. We strive to present the motivations behind the architecture of these tools, including detailed discussion of the subtle technology and circuit concerns that must be addressed in any successful analog or mixed-signal layout tool. Our approach in organizing the chapters of the book has been to present our algo­ rithms as a series of responses to these very real and very difficult analog layout problems. Finally, we present numerous examples of results generated by our algorithms. This research was supported in part by the Semiconductor Research Corpora­ tion, by the National Science Foundation, by Harris Semiconductor, and by the International Business Machines Corporation Resident Study Program. Finally, just for the record: John Cohn was the designer of the KOAN placer; David Garrod was the designer of the ANAGRAM II router (and its predeces­ sor, ANAGRAM I). This book was architected by all four authors, edited by John Cohn and Rob Rutenbar, and produced in finished form by John Cohn.

1 Introduction.- 1.1 Focus.- 1.2 Introduction.- 1.3 Analog Cell Layout: Important Concerns.- 1.4 Semi-Custom Analog Layout Technologies.- 1.5 Layout Strategy.- 1.6 Overview.- 2 Basic Placement.- 2.1 Introduction.- 2.2 Simulated Annealing for Device-Level Placement.- 2.3 Basic Placement Formulation.- 2.4 KOAN Basic Placement Functionality.- 2.5 KOAN Basic Placement Results.- 2.6 Summary.- 3 Topological Placement.- 3.1 Introduction.- 3.2 Modeling Topological Constraints.- 3.3 Placement for Device Matching.- 3.4 Placement for Layout Symmetry.- 3.5 Placement for System-Level Topological Constraints.- 3.6 General Implementation Issues.- 3.7 Topologically-Constrained Results.- 3.8 Summary.- 4 Geometry Sharing Placement.- 4.1 Introduction.- 4.2 Geometry Sharing Optimizations in Analog VLSI Layout.- 4.3 Supporting Geometry Sharing Optimizations.- 4.4 Geometry Sharing Results.- 4.5 Placement Optimization Dynamics.- 4.6 Summary.- 5 Line-Expansion Routing.- 5.1 Line-Expansion Routing.- 5.2 Basic Path Finding.- 5.3 Other Basic Routing Issues.- 5.4 Results.- 5.5 Summary.- 6 Integrated Rerouting.- 6.1 Need for Ripup.- 6.2 Rip-up Methodologies.- 6.3 Integrated Rip-up in ANAGRAM II.- 6.4 Embedding: Controlling Rip-up/Reroute.- 6.5 Summary.- 7 Symmetric Routing.- 7.1 Thermal Matching.- 7.2 Parametric Device Matching.- 7.3 Symmetric Placement.- 7.4 Symmetric Routing: Motivations.- 7.5 Symmetric Routing in ANAGRAM II.- 7.6 Routability Issues in Symmetric Routing.- 7.7 Results.- 7.8 Summary.- 8 Crosstalk Avoidance Routing.- 8.1 Crosstalk Avoidance Routing: Background.- 8.2 Crosstalk Avoidance in ANAGRAM II.- 8.3 Path Finding and Crosstalk Penalties.- 8.4 Results.- 8.5 Summary.- 9 Additional KOAN/ANAGRAM II Results.- 9.1 Introduction.- 9.2 System-Level Overview.- 9.3 Scaling behavior.- 9.4Additional Comparisons with Manual Layout.- 9.5 Technology Remapping.- 9.6 Fabrication Example.- 9.7 Incremental re-spacing.- 9.8 Summary.- 10 Conclusions and Future Work.