The Boundary-Scan Handbook, 1992

Boundary-Scan, formally known as IEEE/ANSI Standard 1149.1-1990, is a collection of design rules applied principally at the integrated circuit (IC) level that allow software to alleviate the growing cost of designing and producing digital systems. The primary benefit of the standard is its ability to transform extremely printed circuit board testing problems that could only be attacked with ad-hoc testing methods into well-structured problems that software can easily and swiftly deal with. The Boundary-Scan Handbook is for professionals in the electronics industry who are concerned with the practical problems of competing successfully in the face of rapid-fire technological change. Since many of these changes affect our ability to do testing and hence cost-effective production, the advent of the 1149.1 standard is rightly looked upon as a major breakthrough. However, there is a great deal of misunderstanding about what to expect of 1149.1 and how to use it. Because of this, The Boundary-Scan Handbook is not a rehash of the 1149.1 standard, nor does it intend to be a tutorial on the basics of its workings. The standard itself should always be consulted for this, being careful to follow supplements issued by the IEEE that clarify and correct it. Rather, The Boundary-Scan Handbook motivates proper expectations and explains how to use the standard successfully.

1: Boundary-Scan Basics and Vocabulary. 1.1 Testing Before Boundary-Scan. 1.2 The Philosophy of 1149.1-1990. 1.3 Basic Architecture. 1.4 Non-Invasive Operational Modes. 1.5 Pin-permission Operational Modes. 1.6 Extensibility. 1.7 Costs and Benefits. 1.8 Other Testability Standards. 2: Boundary-Scan Description Language (BSDL). 2.1 The Scope of BSDL. 2.2 Sturcture of BSDL. 2.3 Entity Descriptions. 2.4 Packages and Package Bodies. 2.5 Writing BSDL. 2.6 Summary. 3: Boundary-Scan Testing. 3.1 Basic Boundary-Scan Testing. 3.2 Testing with Boundary-Scan Chains. 3.3 Summary. 4: Advanced Boundary-Scan Testing. 4.1 DC Parametric IC Tests. 4.2 Sample Mode Tests. 4.3 Concurrent Monitoring. 4.4 Hardware Development Support. 4.5 Non-Scan IC Testing. 4.6 Non-Digital Device Testing. 4.7 Mixed Digital/Analog Testing. 4.8 Multi-Chip Module Testing. 5: Design for Boundary-Scan Testing. 5.1 Integrated Circuit Level DFT. 5.2 Board-Level DFT. 5.3 System-Level DFT. 5.4 Summary. The Future of Boundary-Scan. Appendix. Index.