Logic Synthesis for Low Power VLSI Designs, 1998

Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Logic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints.
Logic Synthesis for Low Power VLSI Designs is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis.

I Background, Terminology, and Power Modeling.- 1 Introduction.- 2 Technology Independent Power Analysis and Modeling.- II Two-level Function Optimization for Low Power.- 3 Two-Level Logic Minimization in CMOS Circuits.- 4 Two-Level Logic Minimization in PLAs.- III Multi-level Network Optimization for Low Power.- 5 Logic Restructuring for Low Power.- 6 Logic Minimization for Low Power.- 7 Technology Dependent Optimization for Low Power.- 8 Post Mapping Structural Optimization for Low Power.- IV Power Optimization Methodology.- 9 POSE: Power Optimization and Synthesis Environment.- V Conclusion.- 10 Concluding Remarks.