Low-Power Deep Sub-Micron CMOS Logic, Softcover reprint of the original 1st ed. 2004
Sub-threshold Current Reduction
The Springer International Series in Engineering and Computer Science Series, Vol. 841

1. 1 Power-dissipation trends in CMOS circuits Shrinking device geometry, growing chip area and increased data-processing speed performance are technological trends in the integrated circuit industry to enlarge chip functionality. Already in 1965 Gordon Moore predicted that the total number of devices on a chip would double every year until the 1970s and every 24 months in the 1980s. This prediction is widely known as "Moore's Law" and eventually culminated in the Semiconductor Industry Association (SIA) technology road map [1]. The SIA road map has been a guide for the in­ dustry leading them to continued wafer and die size growth, increased transistor density and operating frequencies, and defect density reduction. To mention a few numbers; the die size increased 7% per year, the smallest feature sizes decreased 30% and the operating frequencies doubled every two years. As a consequence of these trends both the number of transistors and the power dissi­ pation per unit area increase.In the near future the maximum power dissipation per unit area will be reached. Down-scaling of the supply voltage is not only the most effective way to reduce power dissipation in general it also is a necessary precondition to ensure device reliability by reducing electrical fields and device temperature, to prevent device degradation. A draw-back of this solution is an increased signal propa­ gation delay, which results in a lower data-processing speed performance.

1. Introduction.- 1.1 Power-dissipation trends in CMOS circuits.- 1.2 Overview of present power-reduction solutions.- 1.3 Aim and scope of this book.- 1.4 Organization of the book.- 2. Power Versus Energy.- 2.1 Power considerations.- 2.2 Energy considerations.- 2.3 Conclusions.- 3. Power Dissipation in Digital CMOS Circuits.- 3.1 Thermodynamics of computation.- 3.2 Functional power dissipation.- 3.3 Parasitical power dissipation.- 3.4 Trends in power dissipation.- 3.5 Conclusions.- 4. Reduction of Functional Power Dissipation.- 4.1 Node transition-cycle activity factor.- 4.2 Clock frequency.- 4.3 Transition-cycle energy.- 4.4 Conclusions.- 5. Reduction of Parasitical Power Dissipation.- 5.1 Leakage power dissipation.- 5.2 Short-circuit power dissipation.- 5.3 Need for weak-inversion current reduction.- 5.4 Conclusions.- 6. Weak-Inversion Current Reduction.- 6.1 Classification.- 6.2 Conclusions.- 7. Effectiveness of Weak-Inversion Current Reduction.- 7.1 General effectiveness.- 7.2 Technique-specific effectiveness.- 7.3 Conclusions.- 8. Triple-S Circuit Designs.- 8.1 Process flow.- 8.2 Experimental circuits.- 8.3 Leakage, speed, area and functional power.- 8.4 Practical applications and limitations.- 8.5 Conclusions.- 9. Conclusions.- 10. Summary.- References.

Classifies all power dissipation sources in digital CMOS circuits Provides for a systematic approach of power reduction techniques A clear distinction between power dissipated to perform a calculation in a certain time frame, i.e. functional power dissipation, and power dissipated even when a circuit is idle, i.e. parasitical power dissipation Power dissipation is discussed from a fundamental, quantum mechanical and a practical point of view Theory is accompanied with practical circuit implementations and measurement results