Low Power UWB CMOS Radar Sensors, 2008
Analog Circuits and Signal Processing Series

Language: English

Approximative price 158.24 €

In Print (Delivery period: 15 days).

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Low Power UWB CMOS Radar Sensors
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235 p. · 15.5x23.5 cm · Paperback

Approximative price 158.24 €

Subject to availability at the publisher.

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Low power UWB CMOS radar sensors (Analog circuits & signal processing series) POD
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Low Power UWB CMOS Radar Sensors deals with the problem of designing low cost CMOS radar sensors. The radar sensor uses UWB signals in order to obtain a reasonable target separation capability, while maintaining a maximum signal frequency below 2 GHz. This maximum frequency value is well within the reach of current CMOS technologies. The use of UWB signals means that most of the methodologies used in the design of circuits and systems that process narrow band signals, can no longer be applied.

Low Power UWB CMOS Radar Sensors provides an analysis between the interaction of UWB signals, the antennas and the processing circuits. This analysis leads to some interesting conclusions on the types of antennas and types of circuits that should be used. A methodology to compare the noise performance of UWB processing circuits is also derived. This methodology is used to analyze and design the constituting circuits of the radar transceiver. In order to validate the design methodology a CMOS prototype is designed and experimentally evaluated.

1 Introduction. 2 UWB Signals and Systems. 3 UWB RADAR Receiver Architecture. 4 Digitally Programmable Delay. 5 Transceiver Prototype and Experimental Results. 6 Conclusions. Appendix A: Echo Signals From Moving Targets. Appendix B: Gain and Offset Errors in the S&H due to the MOS Switches. Appendix C: Sigma Delta Modulator. Appendix D: Bond-Wire Parasitic Effects. Appendix E: Oscilloscope Characterization. Index.

Includes a study of the interaction between UWB signals, the antenna and the circuit Includes a design example from system level specifications to transistor level design Introduces a novel digital programmable delay circuit Includes a design example with experimental results