Description
Network-on-Chip
The Next Generation of System-on-Chip Integration
Authors: Kundu Santanu, Chattopadhyay Santanu
Language: EnglishSubjects for Network-on-Chip:
Keywords
Power Consumption; NoC Architecture; Application Mapping on NoC; Swap Sequence; MoT; Complete Binary Tree; 3-D Integration; NoC Design; 3-D NoC Architecture; Bisection Width; ASNoC Synthesis; ILP Formulation; Adaptive Router Architecture Design; Clock Gating; Architecture Design of Network – on- Chip; Head Flit; Asynchronous FIFO Design; Node Degree; Coding Technique; Router Positions; Constructive Heuristics; NoC Topology; Evolution of NoC Architectures; Scan Chains; Flit Size; Column Tree; Flow Control Protocol; Self-similar Traffic; GALS Style of Communication; Root Routers; Core Graph; Interconnection Networks in NoC; Row Tree; Local Reconfiguration Approach; Discrete PSO; NI Module; WH Router; Network-on- Chip Architectures; Mesh-1 Network; NoC Fabric; Gal; NoC Testing; Swap Operator; Permanent Fault Controlling Technique; Localized Traffic Condition; Reconfigurable Computing; Mapped Core; Reconfigurable Network-on-Chip Design; Router Design for NoC; Signal Integrity Issues in NoC; SoC; Standard Low-Power Methods for NoC Links; Standard Low-Power Methods for NoC Routers; Switching Techniques; System-on-Chip; Traffic Modeling; Transient Fault Controlling Technique; Tree-Based Topologies; Unified Coding Framework; VC Router; VC Router Architecture Design; Wormhole Router Architecture Design; Santanu Chattopadhyay
77.28 €
In Print (Delivery period: 14 days).
Add to cart the book of Kundu Santanu, Chattopadhyay SantanuPublication date: 07-2017
· 15.6x23.4 cm · Paperback
166.30 €
In Print (Delivery period: 15 days).
Add to cart the book of Kundu Santanu, Chattopadhyay SantanuPublication date: 12-2014
· 15.6x23.4 cm · Hardback
Description
/li>Contents
/li>Readership
/li>Biography
/li>
Addresses the Challenges Associated with System-on-Chip Integration
Network-on-Chip: The Next Generation of System-on-Chip Integration
Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design.
This text comprises 12 chapters and covers:
- The evolution of NoC from SoC?its research and developmental challenges
- NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces
- The router design strategies followed in NoCs
- The evaluation mechanism of NoC architectures
- The application mapping strategies followed in NoCs
- Low-power design techniques specifically followed in NoCs
- The signal integrity and reliability issues of NoC
- The details of NoC testing strategies reported so far
- The problem of synthesizing application-specific NoCs
- Reconfigurable NoC design issues
- Direction of future research and development in the field of NoC
Network-on-Chip: The Next Generation of System-on-Chip Integration
Introduction. Interconnection Networks in Network-on-Chip. Architecture Design of Network-on-Chip. Evaluation of Network-on-Chip Architectures. Application Mapping on Network-on-Chip. Low-Power Techniques for Network-on-Chip. Signal Integrity and Reliability of Network-on-Chip. Testing of Network-on- Chip Architectures. Application-Specific Network-on-Chip Synthesis. Reconfigurable Network-on-Chip Design. Three-Dimensional Integration of Network-on-Chip. Conclusions and Future Trends. References. Index.
Santanu Kundu received his BTech in instrumentation engineering from Vidyasagar University, Medinipur, West Bengal, India, in 2002. He received his MTech in instrumentation and electronics engineering from Jadavpur University, Kolkata, West Bengal, India, in 2006. Immediately after that he joined the electronics and electrical communication engineering department at the Indian Institute of Technology, Kharagpur, West Bengal, India. He received his PhD in 2011. His research interests include network-on-chip architecture design in 2D and 3D environments, performance and cost evaluation, signal integrity in nanometer regime, fault-tolerant schemes, and power–performance–reliability trade-off. He is currently a system-on-chip (SoC) design engineer at LSI India R&D Pvt. Ltd., Bangalore, Karnataka, India.
Santanu Chattopadhyay