A Pipelined Multi-Core Machine with Operating System Support, 1st ed. 2020
Hardware Implementation and Correctness Proof

Theoretical Computer Science and General Issues Series

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Language: English

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628 p. · 15.5x23.5 cm · Paperback

This work is building on results from the book named ?A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness? by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014.

It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:

? MIPS instruction set architecture (ISA) for application and for system programming

? cache coherent memory system

? store buffers in front of the data caches

? interrupts and exceptions

? memory management units (MMUs)

? pipelined processors: the classical five-stage pipeline is extended by two pipeline

stages for address translation

? local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)

? I/O-interrupt controller and a disk

 

Introductory material.- on hierarchical hardware design.- hardware library.- basic processor design.- pipelining.- cache memory systems.- interrupt mechanism.- self modification, instruction buffer and nondeterministic ISA.- memory management units.- store buffers.- multi-core processors.- advanced programmable interrupt controllers (APICs).- adding a disk.- I/O apic.

Future development based on LNCS 9000 published in 2014

Monograph by well-known experts in the field

Presents construction and correctness proof of the MIPS instruction set architecture