Synthesizable VHDL Design for FPGAs, 2014

The methodology described in this book is the result of many years of research experience in the field of synthesizable VHDL design targeting FPGA based platforms. VHDL was first conceived as a documentation language for ASIC designs. Afterwards, the language was used for the behavioral simulation of ASICs, and also as a design input for synthesis tools. VHDL is a rich language, but just a small subset of it can be used to write synthesizable code, from which a physical circuit can be obtained. Usually VHDL books describe both, synthesis and simulation aspects of the language, but in this book the reader is conducted just through the features acceptable by synthesis tools. The book introduces the subjects in a gradual and concise way, providing just enough information for the reader to develop their synthesizable digital systems in VHDL. The examples in the book were planned targeting an FPGA platform widely used around the world.

Dr. Eduardo Bezerra is a Researcher and Lecturer of Computer Engineering at Universidade Federal de Santa Catarina (UFSC), where he is with the Department of Electrical Engineering since 2010. He received his Ph.D. in Computer Engineering from the University of Sussex (Space Science Centre), England, UK, in 2002. His research interests are in the areas of embedded systems, computer architecture, reconfigurable systems (FPGAs), space applications, software & hardware testing, fault tolerance and microprocessor applications.

Djones Lettnin has Master´s in Electric Engineering at Catholic University of Rio Grande do Sul (2004), Brazil, and Sc.D. in Computer Engineering at the Eberhard Karls University of Tübingen (2009), Germany. In August 2011 he became Professor at Federal University of Santa Catarina, Brazil. Since August 2012 he is first coordinator of the Cadence Academic Network in Latin America. His main interests are in design and functional verification of hardware and embedded software with main focus on: modeling of embedded systems, digital design, verification based on assertions, semiformal and formal verification using model checking.