Durable Phase-Change Memory Architectures Advances in Computers Series
Advances in Computers, Volume 118, the latest volume in this innovative series published since 1960, presents detailed coverage of new advancements in computer hardware, software, theory, design and applications. Chapters in this updated release include Introduction to non-volatile memory technologies, The emerging phase-change memory, Phase-change memory architectures, Inter-line level schemes for handling hard errors in PCMs, Handling hard errors in PCMs by using intra-line level schemes, and Addressing issues with MLC Phase-change Memory.
1. Introduction to Non-volatile Memory Technologies Marjan Asadinia and Hamid Sarbazi-Azad 2. The Emerging Phase-change Memory Marjan Asadinia and Hamid Sarbazi-Azad 3. Phase-change Memory Architectures Marjan Asadinia and Hamid Sarbazi-Azad4. Tolerating More Hard Errors in PCMs Marjan Asadinia and Hamid Sarbazi-Azad 5. Improving the Lifetime of Worn-out Blocks Marjan Asadinia and Hamid Sarbazi-Azad 6. Addressing Issues with MLC Phase-change Memory Marjan Asadinia and Hamid Sarbazi-Azad
Researchers from academic and industry studying high-performance computing and storage systems, and hardware manufacturers producing systems requiring high-performance memory systems
- Gives a comprehensive overlook of new memory technologies, including PCM
- Provides reliability features with an in-depth discussion of physical mechanisms that are currently limiting PCM capabilities
- Covers the work of well-known authors and researchers in the field
- Includes volumes that are devoted to single themes or subfields of computer science
Date de parution : 02-2020
Ouvrage de 146 p.
15x22.8 cm
Thèmes de Durable Phase-Change Memory Architectures :
Mots-clés :
Amorphous phase; Byte-level compression; Chalcogenide material; Crystalline phase; Data block partitioning; Disk storage; Dynamic RAM; Endurance; Energy-efficient memory; Fault model; Frequent value locality; Hard error; Hard error correction; Hard error detection; Hybrid memory; Lifetime; Line-level pairing; Memory bit flip uniformity; Memory block shifting; Memory hierarchy; Multi-level cell PCM; Nonvolatile memory; Page fault and page pairing; PCM read and write techniques; Phase change memory; Phase change memory (PCM); Power consumption; Process variation; Program and verify technique; Reliability; Resistance drift; Resistance partitioning; Scalability; Soft error issues; Static RAM; Variable resistance assignment; Wear-leveling