Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects, Softcover reprint of the original 1st ed. 2017

This book introduces readers to a variety of tools for automatic analog integrated circuit (IC) sizing and optimization. The authors provide a historical perspective on the early methods proposed to tackle automatic analog circuit sizing, with emphasis on the methodologies to size and optimize the circuit, and on the methodologies to estimate the circuit?s performance. The discussion also includes robust circuit design and optimization and the most recent advances in layout-aware analog sizing approaches. The authors describe a methodology for an automatic flow for analog IC design, including details of the inputs and interfaces, multi-objective optimization techniques, and the enhancements made in the base implementation by using machine leaning techniques. The Gradient model is discussed in detail, along with the methods to include layout effects in the circuit sizing. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. An extensive set of application examples is included to demonstrate the capabilities and features of the methodologies described.

Introduces readers to an efficient, multi-objective design methodology and tool for automatic analog IC sizing, which compensates for the effects of process variations Presents an innovative approach to enhance AIDA-C, by embedding statistical knowledge from an automatically generated gradient model into the NSGA-II operators Enables an efficient setup flow, which eases reuse and migration of designs to different specifications and technologies Includes supplementary material: sn.pub/extras