Description
Computer Principles and Design in Verilog HDL
Author: Li Yamin
Language: English
Subject for Computer Principles and Design in Verilog HDL:
Keywords
computer architecture, microprocessor design, industrially important Hardware Description Language (HDL), readily simulate, adjust the operation of each design, industrially relevant skills, computer principles, computer design, Verilog HDL (Hardware Description Language), implement design, computer fundamentals, performance evaluation, digital circuits, computer arithmetic algorithms, Wallace Tree for multiplication, Newton-Raphson algorithm, Goldschmidt algorithm for division and square root, instruction set architecture, ALU design, register file design, single-cycle CPU, multiple-cycle CPU, pipelined CPU designs, interrupts, exceptions, precise interrupts/exceptions, floating-point algorithms, FPU design, and pipelined CPU/FPU design in Verilog HDL, multithreading CPU design in Verilog HDL, memory, cache, virtual memory management, design of CPU/FPU with cache, TLB in Verilog HDL, Multi-core CPU design in Verilog HDL, UART (Universal Asynchronous Receiver Transmitter), PS/2 keyboard and mouse, VGA (Video Graphics Array), I2C series bus PCI, parallel bus interface design in Verilog HDL, high-performance computers, interconnection networks, Verilog HDL source codes, simulation waveforms, CAD/CAE tools
550 p. · 17x24.6 cm · Hardback
Description
/li>Contents
/li>Biography
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Uses Verilog HDL to illustrate computer architecture and microprocessor design, allowing readers to readily simulate and adjust the operation of each design, and thus build industrially relevant skills
- Introduces the computer principles, computer design, and how to use Verilog HDL (Hardware Description Language) to implement the design
- Provides the skills for designing processor/arithmetic/cpu chips, including the unique application of Verilog HDL material for CPU (central processing unit) implementation
- Despite the many books on Verilog and computer architecture and microprocessor design, few, if any, use Verilog as a key tool in helping a student to understand these design techniques
- A companion website includes color figures, Verilog HDL codes, extra test benches not found in the book, and PDFs of the figures and simulation waveforms for instructors
List of Figures xv
List of Tables xxvii
Preface xxix
1 Computer Fundamentals and Performance Evaluation 1
2 A Brief Introduction to Logic Circuits and Verilog HDL 19
3 Computer Arithmetic Algorithms and Implementations 63
4 Instruction Set Architecture and ALU Design 111
5 Single-Cycle CPU Design in Verilog HDL 143
6 Exceptions and Interrupts Handling and Design in Verilog HDL 170
7 Multiple-Cycle CPU Design in Verilog HDL 192
8 Design of Pipelined CPU with Precise Interrupt in Verilog HDL 212
9 Floating-Point Algorithms and FPU Design in Verilog HDL 266
10 Design of Pipelined CPU with FPU in Verilog HDL 323
11 Memory Hierarchy and Virtual Memory Management 353
12 Design of Pipelined CPU with Caches and TLBs in Verilog HDL 386
13 Multithreading CPU and Multicore CPU Design in Verilog HDL 425
14 Input/Output Interface Controller Design in Verilog HDL 443
15 High-Performance Computers and Interconnection Networks 509
Bibliography 536
Index 539
Yamin Li, Professor, Department of Computer Science, Hosei University, Tokyo, Japan.
Professor Li received his PhD in computer science from Tsinghua University in 1989. His research interests include computer arithmetic algorithms, computer architecture, CPU design, and parallel & distributed computing. He is a senior member of the IEEE and a member of the IEEE Computer Society. Professor Li has taught the courses of "Logic Circuit Design", "Assembly Language Programming", "Computer Organization and Design", "CPU Design in Verilog HDL", "Computer Architecture", and "Parallel & Distributed Systems" for more than 20 years, and has used FPGA boards and CAD/CAE tools to teach these courses since 1993. He has published more than 100 journal and conference papers, and developed a square root circuit at low cost and published it in IEEE ICCD'96 and ICCD'97.
