Enhanced Virtual Prototyping, 1st ed. 2021 Featuring RISC-V Case Studies

This book presents a comprehensive set of techniques that enhance all key aspects of a modern Virtual Prototype (VP)-based design flow. The authors emphasize automated formal verification methods, as well as advanced coverage-guided analysis and testing techniques, tailored for SystemC-based VPs and also the associated Software (SW). Coverage also includes VP modeling techniques that handle functional as well as non-functional aspects and also describes correspondence analyses between the Hardware- and VP-level to utilize information available at different levels of abstraction. All approaches are discussed in detail and are evaluated extensively, using several experiments to demonstrate their effectiveness in enhancing the VP-based design flow. Furthermore, the book puts a particular focus on the modern RISC-V ISA, with several case-studies covering modeling as well as VP and SW verification aspects.

Introduction.- Preliminaries.- An Open-Source RISC-V Evaluation Platform.- Formal Verification of SystemC-based Designs using Symbolic Simulation.- Coverage-guided Testing for Scalable Virtual Prototype Verification.- Verification of Embedded Software Binaries using Virtual Prototypes.- Validation of Firmware-Based Power Management using Virtual Prototypes.- Register-Transfer Level Correspondence Analysis.- Conclusion.- Index

Vladimir Herdt received the M.Sc. degree in computer science from the University of Bremen, Germany, in 2014. Afterwards, he started as a PhD student with the Group of Computer Architecture. In 2020, he received the Dr.-Ing. degree in computer science from the University of Bremen. Since 2020, he is Senior Researcher at the Cyber-Physical Systems department of the German Research Center for Artificial Intelligence (DFKI). His current research interests include virtual prototyping as well as verification and analysis techniques with a particular focus on RISC-V. In these areas he published more than 25 peer-reviewed journal and conference papers. He is recipient of the Springer BestMasters award. 

Daniel Große received the Dr.-Ing. degree in computer science from the University of Bremen in 2008. He remained as a Post-Doctoral Researcher with the Group of Computer Architecture, University of Bremen. In 2010, he was a substitute Professor for computer architecture with Albert‐Ludwigs University, Freiburg im Breisgau, Germany. From 2013 to 2014, he was the CEO of the EDA start-up solvertec focusing on automated debugging techniques. Since 2015, he has been a Senior Researcher with the University of Bremen and at the German Research Center for Artificial Intelligence (DFKI), and also the Scientific Coordinator of the Graduate School of System Design, funded within the German Excellence Initiative. Since July 2020, he is a full professor at the Johannes Kepler University Linz, Austria, where he is the head of the group from Complex Systems. His current research interests include verification, virtual prototyping, debugging, and synthesis. He published over 130 papers in peer-reviewed journals and conferences in the above areas. Dr. Große served in program committees of numerous conferences, including DAC, DATE, ICCAD, CODES+ISSS, FDL, and MEMOCODE. He received best paper awards at FDL 2007, DVCon Europe 2018, and ICCAD 2018. He is an IEEE Senior

Provides a comprehensive set of techniques to enhance all key aspects of a Virtual Prototype (VP)-based design flow

Includes automated formal verification methods and advanced coverage-guided testing techniques, tailored for SystemC-based VPs

Describes efficient, coverage-guided test generation methods for VP-based functional and non-functional software (SW) analysis and verification

Includes correspondence analyses to utilize information between different abstraction levels in the design flow

Uses several VP and SW verification case-studies that target the modern RISC-V ISA