Fast Simulation of Computer Architectures, Softcover reprint of the original 1st ed. 1995

Chapters in Fast Simulation of Computer Architectures cover topics such as how to collect traces, emulate instruction sets, simulate microprocessors using execution-driven techniques, evaluate memory hierarchies, apply statistical sampling to simulation, and how to augment simulation with performance bound models. The chapters have been written by many of the leading researchers in the area, in a collaboration that ensures that the material is both coherent and cohesive.
Audience: Of tremendous interest to practising computer architect designers seeking timely solutions to tough evaluation problems, and to advanced upper division undergraduate and graduate students of the field. Useful study aids are provided by the problems at the end of Chapters 2 through 8.

1. Introduction; T. M. Conte, C. E. Gimarc. 2. SHADE: A Fast Instruction-Set Simulator for Execution Profiling; B. Cmelik, D. Keppel. 3. Instrumentation Tools; J. Pierce et al. 4. Stack-Based Single-Pass Cache Simulation; T. M. Conte. 5. Non-Stack Single-Pass Simulation; R. A. Sugumar, S. G. Abraham. 6. Execution Driven Simulation of Shared Memory Multiprocessors; B. Boothe. 7. Sampling for Cache and Processor Simulation; K. N. Menezes. 8. Performance Bounds for Rapid Computer System Evaluation; B. Mangione-Smith. Index.