Hardware IP Security and Trust, Softcover reprint of the original 1st ed. 2017
This book provides an overview of current Intellectual Property (IP) based System-on-Chip (SoC) design methodology and highlights how security of IP can be compromised at various stages in the overall SoC design-fabrication-deployment cycle. Readers will gain a comprehensive understanding of the security vulnerabilities of different types of IPs. This book would enable readers to overcome these vulnerabilities through an efficient combination of proactive countermeasures and design-for-security solutions, as well as a wide variety of IP security and trust assessment and validation techniques. This book serves as a single-source of reference for system designers and practitioners for designing secure, reliable and trustworthy SoCs.
Part I. Introduction.- Chapter 1.Security and Trust Vulnerabilities in Third-party IPs.- PArt II.Trust Analysis.- Chapter 2.Security Rule Check.- Chapter 3.Digital Circuit Vulnerabilities to Hardware Trojans.- Chapter 4.Code Coverage Analysis for IP Trust Verification.- Chapter 5.Analyzing Circuit Layout to Probing Attack.- Chapter 6.Testing of Side Channel Leakage of Cryptographic IPs: Metrics and Evaluations.- Part III.- Effective Countermeasures.- Chapter 7.Hardware Hardening Approaches using Camouflaging, Encryption and Obfuscation.- Chapter 8.A Novel Mutating Runtime Architecture for Embedding Multiple Countermeasures Against Passive Side Channel Attacks.- Part IV.- Chapter 9.Validation of IP Security and Trust.- Chapter 10.IP Trust Validation using Proof-carrying Hardware.- Chapter 11. Hardware Trust Verification.- Chapter 12.Verification of Unspecified IP Functionality.- Chapter 13.Verifying Security Properties in Modern SoCs using Instruction-level Abstractions.- Chapter 14. Test Generation for Detection of Malicious Parametric Variations.- Part V. Conclusions.- Chapter 15.The Future of Trustworthy SoC Design.
Prabhat Mishra is an Associate Professor in the Department of Computer and Information Science and Engineering (CISE) at the University of Florida (UF) where he leads the CISE Embedded Systems Lab. His research interests include design automation of embedded systems, energy-aware computing, reconfigurable architectures, hardware security and trust, system validation and verification, and post-silicon debug.
He received his B.E. from Jadavpur University, Kolkata in 1994, M.Tech. from the Indian Institute of Technology, Kharagpur in 1996, and Ph.D. from the University of California, Irvine in 2004 -- all in Computer Science and Engineering. Prior to joining University of Florida, he spent several years in various companies including Intel, Motorola, Synopsys and Texas Instruments. He has published four books and more than 100 research articles in premier international journals and conferences. His research has been recognized by several awards including the NSF CAREER Award from the National Science Foundation, IBM Faculty Award, two best paper awards (VLSI Design 2011 and CODES+ISSS 2003), five best paper nominations (including DAC'09 and DATE'12), and 2004 EDAA Outstanding Dissertation Award from the European Design Automation Association. He has also received the 2007 International Educator of the Year Award from the UF College of Engineering for his international research and teaching contributions.Swarup Bhunia received his B.E. (Hons.) from Jadavpur University, Kolkata, India, and the M.Tech. degree from the Indian Institute of Technology (IIT), Kharagpur. He received his Ph.D. from Purdue University, IN, USA, in 2005. Currently, Dr. Bhunia is a professor in the department of Electrical and Computer Engineering at University of Florida, Gainesville, FL, USA. Earlier, Dr. Bhunia has served as the T. and A. Schroeder associate professor of Electrical Engineering and Computer Science at Case Western Reserve University, Cleveland, OH,
Date de parution : 01-2017
Ouvrage de 353 p.
15.5x23.5 cm
Date de parution : 07-2018
Ouvrage de 353 p.
15.5x23.5 cm
