Harnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms, 1st ed. 2019 A Cross-layer Approach

This book describes the state-of-the art of industrial and academic research in the architectural design of heterogeneous, multi/many-core processors. The authors describe methods and tools to enable next-generation embedded and high-performance heterogeneous processors to confront cost-effectively the inevitable variations by providing Dependable-Performance: correct functionality and timing guarantees throughout the expected lifetime of a platform under thermal, power, and energy constraints. Various aspects of the reliability problem are discussed, at both the circuit and architecture level, the intelligent selection of knobs and monitors in multicore platforms, and systematic design methodologies. The authors demonstrate how new techniques have been applied in real case studies from different applications domain and report on results and conclusions of those experiments.

•          Enables readers to develop performance-dependableheterogeneous multi/many-core architectures
  
•          Describes system software designs that support high performance dependability requirements
  
•          Discusses and analyzes low level methodologies to tradeoff conflicting metrics, i.e. power, performance, reliability and thermal management
  
•          Includes new application design guidelines to improve performance dependability
  

Introduction.- Multi-Many core Systems.- Reliability Issues.- HARPA Multi-layer METHODOLOGY: HARPA OS + HARPA RTE.- Reliability and mitigation strategies in HARPA: Modeling.- Reliability and mitigation strategies in HARPA: Mitigation.- Knobs/Monitors.- Event-based Thermal Control.- Power aware design of On-chip communication.- OS –Based Management.- Sensing application.- FLOREON application.- Landslide application.- Conclusions.

William Fornaciari is Associate Professor at Politecnico di Milano, Dipartimento di Elettronica e Informazione. He published six books and over 150 papers in international journals and conference proceedings, collecting five best paper awards, one certification of appreciation from IEEE and holds two international patents on low power design solutions. Since 1993 he is member of program and scientific committees and chair of international conferences in the field of computer architectures, EDA and system-level design. Since 1997 has been involved in 13 EU-funded international projects and he has been part of the pool of experts of the Call For Tender No.964-2005 – WING – Watching IST INnovation and knowledge, studying the impact of FP5 and FP6 expenditure for the EC, in the perspective to support the identification of FP7 and Horizon2020 research directions.

Recently, he participated to the MULTICUBE project for design space exploration and to the IP WASP on wireless sensor networks. In FP7 he has been workpackage leader for the IP COMPLEX project and Project Technical Manager of 2PARMA and also contributes to the Artemis SMECY project. Currently, still in FP7, he is project coordinator of the project HARPA on run-time management t