Description
High-Speed Decoders for Polar Codes, 1st ed. 2017
Authors: Giard Pascal, Thibeault Claude, Gross Warren J.
Language: English
Subjects for High-Speed Decoders for Polar Codes:
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Publication date: 05-2018
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Publication date: 09-2017
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Description
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A new class of provably capacity achieving error-correction codes, polar codes are suitable for many problems, such as lossless and lossy source coding, problems with side information, multiple access channel, etc.
The first comprehensive book on the implementation of decoders for polar codes, the authors take a tutorial approach to explain the practical decoder implementation challenges and trade-offs in either software or hardware. They also demonstrate new trade-offs in latency, throughput, and complexity in software implementations for high-performance computing and GPGPUs, and hardware implementations using custom processing elements, full-custom application-specific integrated circuits (ASICs), and field-programmable-gate arrays (FPGAs).
Presenting a good overview of this research area and future directions, High-Speed Decoders for Polar Codes is perfect for any researcher or SDR practitioner looking into implementing efficient decoders for polar codes, as well as students and professors in a modern error correction class. As polar codes have been accepted to protect the control channel in the next-generation mobile communication standard (5G) developed by the 3GPP, the audience includes engineers who will have to implement decoders for such codes and hardware engineers designing the backbone of communication networks.1 Polar Codes.- 2 Fast Low-Complexity Hardware Decoders for Low-Rate Polar Codes.- 3 Low-Latency Software Polar Decoders.- 4 Unrolled Hardware Architectures for Polar Decoders.- 5 Multi-mode Unrolled Polar Decoding.- 6 Conclusion and Future Work.- References.- Index.
Maintains a tutorial nature clearly articulating the problems met when implementing a polar decoder, and incrementally develops various novel solutions
A comprehensive evaluation of software implementation techniques of polar code decoders, targeting modern desktop and embedded processors and general-purpose graphical processing units (GPGPUs)
A comprehensive evaluation of hardware implementation algorithms and architectures targeting both field-programmable-gate arrays (FPGAs) and application-specific-integrated circuits (ASICs)
Both the software and hardware implementation evaluations expose the trade-offs in terms of latency, throughput and complexity
Includes supplementary material: sn.pub/extras
