Introduction to SystemVerilog, 1st ed. 2021

This book provides a hands-on, application-oriented guide to the entire IEEE standard 1800 SystemVerilog language. Readers will benefit from the step-by-step approach to learning the language and methodology nuances, which will enable them to design and verify complex ASIC/SoC and CPU chips. The author covers the entire spectrum of the language, including random constraints, SystemVerilog Assertions, Functional Coverage, Class, checkers, interfaces, and Data Types, among other features of the language. Written by an experienced, professional end-user of ASIC/SoC/CPU and FPGA designs, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the complex task of multi-million gate ASIC designs.

• Provides comprehensive coverage of the entire IEEE standard SystemVerilog language;
• Covers important topics such as constrained random verification, SystemVerilog Class, Assertions, Functional coverage, data types, checkers, interfaces, processes and procedures, among other language features;
• Uses easy to understand examples and simulation logs; examples are simulatable and will be provided online;
• Written by an experienced, professional end-user of ASIC/SoC/CPU and FPGA designs.

Introduction.- Data Types.- Arrays.- Queues.- Structures.- Packages.- Class.- SystemVerilog 'module'.- SystemVerilog 'program'.- Interfaces.- Operators.- Constrained Random Test Generation and Verification.- SystemVerilog Assertions.- Functional Coverage.- SystemVerilog Processes.- Procedural programming statements.- Processes.- Tasks and Functions.- Clocking Blocks.- Checkers.- Inter-process communication and synchronization.- Utility System tasks and functions.

Ashok Mehta is an ASIC/CPU design and verification engineer with over 30 years of experience in the semiconductor industry. He has worked at companies such as DEC, Data General, Intel, Applied Micro and TSMC. He was an early member of the Verilog technical subcommittees. He is the holder of 19 US Patents in the field of ASIC and 3DIC design and verification. He is also the author of two popular books, one on "SystemVerilog Assertions and Functional Coverage" and second on "ASIC Functional Design Verification – A guide to technologies and methodologies". His current interest include 3DIC semiconductor design verification, System Level Modeling (Virtual Platform) and verification methodologies in general.