Nanometer Variation-Tolerant SRAM, 2013
Circuits and Statistical Design for Yield

Language: English

105.49 €

Subject to availability at the publisher.

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Nanometer Variation-Tolerant SRAM
172 p. · 15.5x23.5 cm · Paperback

105.49 €

Subject to availability at the publisher.

Add to cartAdd to cart
Nanometer variation-tolerant SRAM statistical design for yield. Circuits and statistical design for yield
172 p. · 15.5x23.5 cm · Hardback

Variability is one of the most challenging obstacles for IC design in the nanometer regime.  In nanometer technologies, SRAM show an increased sensitivity to process variations due to low-voltage operation requirements, which are aggravated by the strong demand for lower power consumption and cost, while achieving higher performance and density.  With the drastic increase in memory densities, lower supply voltages, and higher variations, statistical simulation methodologies become imperative to estimate memory yield and optimize performance and power.

This bookis an invaluable reference on robust SRAM circuits and statistical design methodologies for researchers and practicing engineers in the field of memory design. It combines state of the art circuit techniques and statistical methodologies to optimizeSRAM performance and yield in nanometer technologies.  

  • Provides comprehensive review of state-of-the-art, variation-tolerant SRAM circuit techniques;
  • Discusses Impact of device related process variations and how they affect circuit and system performance, from a design point of view;
  • Helps designers optimize memory yield, with practical statistical design methodologies and yield estimation techniques.
Introduction.- Variability in Nanometer Technologies and Impact on SRAM.- Variarion-Tolerant SRAM Write and Read Assist Techniques.- Reducing SRAM Power using Fine-Grained Wordline Pulse Width Control.- A Methodology for Statistical Estimation of Read Access Yield in SRAMs.- Characterization of SRAM Sense Amplifier Input Offset for Yield Prediction.
Provides comprehensive review of state-of-the-art, variation-tolerant SRAM circuit techniques Discusses Impact of device related process variations and how they affect circuit and system performance, from a design point of view Helps designers optimize memory yield, with practical statistical design methodologies and yield estimation techniques Includes supplementary material: sn.pub/extras