Parallel Algorithms and Architectures for DSP Applications, Softcover reprint of the original 1st ed. 1991
The Springer International Series in Engineering and Computer Science Series, Vol. 149

Over the past few years, the demand for high speed Digital Signal Proces­ sing (DSP) has increased dramatically. New applications in real-time image processing, satellite communications, radar signal processing, pattern recogni­ tion, and real-time signal detection and estimation require major improvements at several levels; algorithmic, architectural, and implementation. These perfor­ mance requirements can be achieved by employing parallel processing at all levels. Very Large Scale Integration (VLSI) technology supports and provides a good avenue for parallelism. Parallelism offers efficient sohitions to several problems which can arise in VLSI DSP architectures such as: 1. Intermediate data communication and routing: several DSP algorithms, such as FFT, involve excessive data routing and reordering. Parallelism is an efficient mechanism to minimize the silicon cost and speed up the pro­ cessing time of the intermediate middle stages. 2. Complex DSP applications: the required computation is almost doubled. Parallelism will allow two similar channels processing at the same time. The communication between the two channels has to be minimized. 3. Applicatilm specific systems: this emerging approach should achieve real-time performance in a cost-effective way. 4. Testability and fault tolerance: reliability has become a required feature in most of DSP systems. To achieve such property, the involved time overhead is significant. Parallelism may be the solution to maintain ac­ ceptable speed performance.

1. Parallel Architectures for Iterative Image Restoration.- 2. Perfect Shuffle Communications in Optically Interconnected Processor Arrays.- 3. Experiments with Parallel Fast Fourier Transforms.- 4. Fault-Tolerance for Parallel Adaptive Beamforming.- 5. Parallel Computation of Fan Beam Back-Projection Reconstruction Algorithm in Computed Tomography.- 6. Affine Permutations of Matrices on Mesh-Connected Arrays.- 7. Architectures for Statically Scheduled Dataflow.- 8. Design of Asynchronous Parallel Architectures.- 9. Implementation of Multilayer Neural Networks on Parallel Programmable Digital Computers.- 10. Implementation of Sparse Neural Networks on Fixed Size Arrays.