Progress in VLSI Design and Test, 2012
16th International Symposium on VSLI Design and Test, VDAT 2012, Shipur, India, July 1-4, 2012, Proceedings
Theoretical Computer Science and General Issues Series

This book constitutes the refereed proceedings of the 16th International Symposium on VSLI Design and Test, VDAT 2012, held in Shibpur, India, in July 2012. The 30 revised regular papers presented together with 10 short papers and 13 poster sessions were carefully selected from 135 submissions. The papers are organized in topical sections on VLSI design, design and modeling of digital circuits and systems, testing and verification, design for testability, testing memories and regular logic arrays, embedded systems: hardware/software co-design and verification, emerging technology: nanoscale computing and nanotechnology.

Lower Power 1.-An Efficient High Frequency and Low Power Analog Multiplier in Current Domain.-Design of Push-Pull Dynamic Leaker Circuit for a Low Power Embedded Voltage Regulator.-Power Modeling of Power Gated FSM and Its Low Power Realization by Simultaneous Partitioning and State Encoding Using Genetic Algorithm.-Analog VLSI Design I.-Design and Implementation of a Linear Feedback Shift Register Interleaver for Turbo Decoding.-Low Complexity Encoder for Crosstalk Reduction in RLC Modeled Interconnects .-Analog Performance Analysis of Dual-k Spacer Based Underlap FinFET.-Test and Verification I Implementation of Gating Technique with Modified Scan Flip-Flop for Low Power Testing of VLSI Chips.-Post-bond Stack Testing for 3D Stacked IC.-Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker.-Design Techniques I.-Design of High Speed Vedic Multiplier for Decimal Number System.-An Efficient Test Design for CMPs Cache Coherence Realizing MESI Protocol .-An Efficient High Speed Implementation of Flexible Characteristic-2 Multipliers on FPGAs.-Algorithms and Applications I.-Arithmetic Algorithms for Ternary Number System.-SOI MEMS Based Over-Sampling Accelerometer Design with ΔΣ Output .-Design Optimization of a Wide Band MEMS Resonator for Efficient Energy Harvesting.-Lower Power II Ultra-Low Power Sub-threshold SRAM Cell Design to Improve Read Static Noise Margin.-Workload Driven Power Domain Partitioning.-Implementation of a New Offset Generator Block for the Low-Voltage, Low-Power Self Biased Threshold Voltage Extractor Circuit.-Analog VLSI Design II A High Speed, Low Jitter and Fast Acquisition CMOS Phase Frequency Detector for Charge Pump PLL.-ILP Based Approach for Input Vector Controlled (IVC) Toggle in Combinational Circuits.-Comparison of OpAmp Based and Comparator Based Switched Capacitor Filter.-Test and Verification II Effect of Malicious Hardware Logic on Circuit Reliability.-A Modified Scheme for Simultaneous Reduction of Test Data Volume and Testing Power .-Reusable and Scalable Verification Environment for Memory Controllers.-Design Techniques II Design of a Fault-Tolerant Conditional Sum Adder.-SEU Tolerant Robust Latch Design .-Design of Content Addressable Memory Architecture Using Carbon Nanotube Field Effect Transistors.-Algorithms and Applications II.-High-Speed Unified Elliptic Curve Cryptosystem on FPGAs Using Binary Huff Curves .-A 4 × 20 Gb/s 29-1 PRBS Generator for Testing a High-Speed DAC in 90nm CMOS Technology.-VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF (2m) Using Dual Bases .-Emerging Technologies.-A Synthesis Method for Quaternary Quantum Logic Circuits.-On the Compact Designs of Low Power Reversible Decoders and Sequential Circuits.-Delay Uncertainty in Single- and Multi-Wall Carbon Nanotube Interconnects.-Algorithms and Applications III.-A Fast FPGA Based Architecture for Sobel Edge Detection.-Speech Processor Design for Cochlear Implants.-An Efficient Technique for Longest Prefix Matching in Network Routers.-NoC and Physical Design A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase Cuts.-Test Data Compression for NoC Based SoCs Using Binary Arithmetic Operations .-Particle Swarm Optimization Based BIST Design for Memory Cores in Mesh Based Network-on-Chip.-Poster Presentation An Efficient Multiplexer in Quantum-dot Cellular Automata.-Integrated Placement and Optimization Flow for Structured and Regular Logic.-A Novel Symbol Estimation Algorithm for LTE Standard.-Impact of Dummy Poly on the Process-Induced Mechanical Stress Enhanced Circuit Performance.-A Novel Approach to Voltage-Drop Aware Placement in Large SoCs in Advanced Technology Nodes.-Design and Implementation of Efficient Vedic Multiplier Using Reversible Logic .-Design of Combinational and Sequential Circuits Using Novel Feed through Logic.-Efficient FPGA Implementation of Montgomery Multiplier Using DSP Blocks.-Independent Gate SRAM Based on Asymmetric Gate to Source/Drain Overlap-Underlap Device FinFET.-VLSI Architecture for Spatial Domain Spread Spectrum Image.-Watermarking Using Gray-Scale Watermark .-A Photonic Network on Chip with CDMA Links.-Simulation Study of an Ultra Thin Body Silicon On Insulator Tunnel Field Effect Transistor.-Routing in NoC on Diametrical 2D Mesh Architecture.-Invited Talk Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology (Invited Paper) .-Power Problems in VLSI Circuit Testing.-