Routing Algorithms in Networks-on-Chip, Softcover reprint of the original 1st ed. 2014
Coordonnateurs : Palesi Maurizio, Daneshtalab Masoud
Part I Performance Improvement.- Basic Concepts on On-Chip Networks.- A Heuristic Framework for Designing and Exploring Deterministic Routing Algorithm for NoCs.- Run-Time Deadlock Detection.- The Abacus Turn Model.- Learning-based Routing Algorithms for on-Chip Networks.- Part II Multicast Communication.- Efficient and Deadlock-Free Tree-based Multicast Routing Method for Network-on-Chip.- Path-based Multicast Routing for 2D and 3D Mesh Networks.- Part III Fault Tolerance and Reliability.- Fault-Tolerant Routing Algorithms in Networks-on-Chip.- Reliable and Adaptive Algorithms for 2D and 3D Networks-on-Chip.
Ouvrage de 410 p.
15.5x23.5 cm
Ouvrage de 410 p.
15.5x23.5 cm
Thèmes de Routing Algorithms in Networks-on-Chip :
Mots-clés :
Adaptive Routing in Network on Chip; Network on Chip; Network on Chip Routing Architecture; On-Chip Communication Architecture; Routing Algorithms for Intel 80-Core Chip; Routing Algorithms for Manycore Chips; Routing Algorithms for NXP Athereal; Routing Algorithms for Network on Chip; Routing Algorithms for ST Spidergon; Routing Algorithms for TILERA 100-Core Chip