System Level Design from HW/SW to Memory for Embedded Systems, Softcover reprint of the original 1st ed. 2017
5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, Foz do Iguaçu, Brazil, November 3-6, 2015, Proceedings
IFIP Advances in Information and Communication Technology Series, Vol. 523

Coordinators: Götz Marcelo, Schirner Gunar, Wehrmeister Marco Aurélio, Al Faruque Mohammad Abdullah, Rettberg Achim

Language: English

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System Level Design from HW/SW to Memory for Embedded Systems
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Approximative price 82.29 €

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System Level Design from HW/SW to Memory for Embedded Systems
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This book constitutes the refereed proceedings of the 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, held in Foz do Iguaçu, Brazil, in November 2015.

The 18 full revised papers presented were carefully reviewed and selected from 25 submissions. The papers present a broad discussion on the design, analysis and verification of embedded and cyber-physical systems including design methodologies, verification, performance analysis, and real-time systems design. They are organized in the following topical sections: cyber-physical systems, system-level design; multi/many-core system design; memory system design; and embedded HW/SW design and applications.