Terahertz Planar Antennas for Next Generation Communication, 2014

Kumud Ranjan Jha passed the Under-Graduation and Post-Graduation Examinations in the Electronics and Communication Engineering branch in 1999 and 2007, respectively. Since 2007, he is an Assistant Professor in Shri Mata Vaishno Devi University, Katra, Jammu and Kashmir, India, and before joining this University, he has served in the Indian Air Force.  In 2012, he was awarded with the Ph.D. Degree from Jaypee University of Information Technology, Solan, Himachal Pradesh, India and subsequently, in the same year while working on the concept of the gain and directivity enhancement of the Planar Terahertz Antennas, he was awarded with the Raman Fellowship for one year for the Post-Doctoral Study in United States of America from the University Grant Commission, Government of India, New Delhi, India. He is also a visiting professor to San Diego State University, California, USA. He has published a number of peer reviewed research articles in the International Journals and Conferences. His area of research is Microwave/RF passive component design and Terahertz Electronics for the future wireless communication.

Professor Ghanshyam Singh: received PhD degree in Electronics Engineering from the Indian Institute of Technology, Banaras Hindu University, Varanasi, India, in 2000. He was associated with Central Electronics Engineering Research Institute, Pilani, and Institute for Plasma Research, Gandhinagar, India, respectively, where he was Research Scientist. He had also worked as an Assistant Professor at Electronics and Communication Engineering Department, Nirma University of Science and Technology, Ahmedabad, India. He was a Visiting Researcher at the Seoul National University, Seoul, S. Korea. At present, he is Professor with the Department of Electronics and Communication Engineering, Jaypee University of Information Technology, Wakanaghat, Solan, India. He is an author/co-author of more than 180 scientific papers of the refereed Journal and International Confe

Provides a complete and concise introduction to SRAM bitcell design and analysis

Offers techniques to face nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis

Includes simulation set-ups for extracting different design metrics for CMOS technology and emerging devices

Emphasizes different trade-offs for achieving the best possible SRAM bitcell design

Includes supplementary material: sn.pub/extras