Description
The Verilog® Hardware Description Language (5th Ed., 5th ed. 2002. Softcover reprint of the original 5th ed. 2002)
Language: EnglishSubjects for The Verilog® Hardware Description Language:
The Verilog® Hardware Description Language (5th Ed.)
Publication date: 02-2014
382 p. · 15.5x23.5 cm · Paperback
Publication date: 02-2014
382 p. · 15.5x23.5 cm · Paperback
The verilog hardware description language
Publication date: 06-2002
382 p. · 15.5x23.5 cm · Hardback
Publication date: 06-2002
382 p. · 15.5x23.5 cm · Hardback
Description
/li>Contents
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xv From the Old to the New xvii Acknowledgments xxi 1 Verilog ? A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 11 Behavioral Modeling of Combinational Circuits Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 14 Procedural Modeling of Clocked Sequential Circuits Modeling Finite State Machines 15 Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment ("
Verilog — A Tutorial Introduction.- Logic Synthesis.- Behavioral Modeling.- Concurrent Processes.- Module Hierarchy.- Logic Level Modeling.- Cycle-Accurate Specification.- Advanced Timing.- User-Defined Primitives.- Switch Level Modeling.- Projects.
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