Description
Wafer-Level Chip-Scale Packaging, Softcover reprint of the original 1st ed. 2015
Analog and Power Semiconductor Applications
Authors: Qu Shichun, Liu Yong
Language: EnglishSubjects for Wafer-Level Chip-Scale Packaging:
158.24 €
Subject to availability at the publisher.
Add to cart the print on demand of Qu Shichun, Liu YongSupport: Print on demand
322 p. · 15.5x23.5 cm · Hardback
Description
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Chapter 1. Demand and Challenges for Wafer Level Analog and Power Packaging.- Chapter 2. Fan-In Analog Wafer Level Chip Scale Package.- Chapter 3. Fan-Out Analog Wafer Level Chip Scale Package.- Chapter 4. Wafer Level Analog Chip Scale Package Stackable Design.- Chapter 5. Wafer Level Discrete Power MOSFET Package Design.- Chapter 6. Wafer Level Packaging TSV/Stack die for Integration of Analog and Power Solution.- Chapter 7. Thermal Management, Design, Analysis for WLCSP.- Chapter 8. Electrical and Multi-Physics Simulations for Analog and Power WLCSP.- Chapter 9. WLCSP Typical Assembly Process.- Chapter 10. WLCSP Typical Reliability and Test.