Esd - circuits and devices

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Language: English
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456 p. · Hardback
The scaling of semiconductor devices from sub-micron to nanometer dimensions is driving the need for understanding the design of electrostatic discharge (ESD) circuits, and the response of these integrated circuits (IC) to ESD phenomena. /a> ESD Circuits and Devices provides a clear insight into the layout and design of circuitry for protection against electrical overstress (EOS) and ESD. With an emphasis on examples, this text: explains ESD buffering, ballasting, current distribution, design segmentation, feedback, coupling, and de-coupling ESD design methods, outlines the fundamental analytical models and experimental results for the ESD design of MOSFETs and diode semiconductor device elements, with a focus on CMOS, silicon on insulator (SOI), and Silicon Germanium (SiGe) technology, focuses on the ESD design, optimization, integration and synthesis of these elements and concepts into ESD networks, as well as applying within the off-chip driver networks, and on-chip receivers, and highlights state-of-the-art ESD input circuits, as well as ESD power clamps networks. Continuing the authors series of books on ESD, this book will be an invaluable reference for the professional semiconductor chip and system ESD engineer. Semiconductor device and process development, quality, reliability and failure analysis engineers will also find it an essential tool. In addition, both senior undergraduate and graduate students in microelectronics and IC design will find its numerous examples useful.
About the Author.

Preface.

Acknowledgments.

Chapter 1: Electrostatic Discharge.

1.1 Electricity and Electrostatics Discharge.

1.2 Fundamental Concepts of ESD Design.

1.3 Time Constants.

1.4 Capacitance, Resistance and Inductance and ESD.

1.5 Rules of Thumb and ESD.

1.6 Lumped versus Distributed Analysis and ESD.

1.7 ESD Metrics and Figures of Merit.

1.8 Twelve Steps to Building an ESD Strategy.

1.9 Summary and Closing Comments.

Problems.

References.

Chapter 2: Design Synthesis.

2.1 Synthesis and Architecture of a Semiconductor Chip for ESD Protection.

2.2 Electrical and Spatial Connectivity.

2.3 ESD, Latchup, and Noise.

2.4 Interface Circuits and ESD Elements.

2.5 ESD Power Clamps Networks.

2.6 ESD Rail to Rail Devices.

2.7 Guard Rings.

2.8 Pads, Floating Pads, and No Connect Pads.

2.9 Structures Under Bond Pads.

2.10 Summary and Closing Comments.

Problems.

References.

Chapter 3: Electrostatic Discharge (ESD) Design: MOSFET Design.

3.1 Basic ESD Design Concepts.

3.2 ESD MOSFET Design: Channel Width.

3.3 ESD MOSFET Design: Contact.

3.4 ESD MOSFET Design: Metal Distribution.

3.5 ESD MOSFET Design: Silicide Masking.

3.6 ESD MOSFET Design: Series Cascode Configurations.

3.7 ESD MOSFET Design: Multi Finger Design Integration of Coupling and Ballasting Techniques.

3.8 ESD MOSFET Design: Enclosed Drain Design Practice.

3.9 ESD MOSFET Interconnect Ballasting Design.

3.10 ESD MOSFET Design: Source and Drain Segmentation.

3.11 Summary and Closing Comments.

Problems.

References.

Chapter 4: Electrostatic Discharge (ESD) Design: Diode Design.

4.1 ESD Diode Design: ESD Basic.

4.2 ESD Diode Design: Anode.

4.3 ESD Diode Design: Interconnect Wiring.

4.4 ESD Diode Design: Polysilicon Bound Diode Designs.

4.5 ESD Diode Design: n Well Diode Design.

4.6 ESD Diode Design: nþ,/p Substrate Diode Design.

4.7 ESD Diode Design: Diode String.

4.8 ESD Diode Design: Triple Well Diodes.

4.9 ESD Design: BiCMOS ESD Design.

4.10 Summary and Closing Comments.

Problems.

References.

Chapter 5: Silicon on Insulator (SOI) ESD Design.

5.1 SOI ESD Basic Concepts.

5.2 SOI ESD Design: MOSFET with Body Contact (T Shaped Layout).

5.3 SOI ESD Design: SOI Lateral Diode Structure.

5.4 SOI ESD Design: Buried Resistors (BR) Elements.

5.5 SOI ESD Design: SOI Dynamic Threshold MOSFET (DTMOS).

5.6 SOI ESD Design: Dual Gate (DG) MOSFETs.

5.7 SOI ESD Design: FinFET Structure.

5.8 SOI ESD Design: Structures in the Bulk Substrate.

5.9 SOI ESD Design: SOI To Bulk Contact Structures.

5.10 Summary and Closing Comments.

Problems.

References.

Chapter 6: Off Chip Drivers (OCD) and ESD.

6.1 Off Chip Drivers (OCD).

6.2 Off Chip Drivers: Mixed Voltage Interface.

6.3 Off Chip Drivers Self Bias Well OCD Networks.

6.4 Off Chip Drivers: Programmable Impedance (PIMP) OCD Networks.

6.5 Off Chip Drivers: Universal OCDs.

6.6 Off Chip Drivers: Gate Array OCD Design.

6.7 Off Chip Drivers: Gate Modulated Networks.

6.8 Off Chip Driver ESD Design: Integration of Coupling and Ballasting Techniques.

6.9 Off Chip Driver ESD Design: Substrate Modulated...